The present invention relates to integrated circuits. More particularly, the present invention relates to improved methods and apparatus for forming isolation barriers in integrated circuits.
In a typical integrated circuit (IC), a large number of active devices such as transistors are provided on a semiconductor wafer, e.g., a silicon wafer. For MOS (metal oxide semiconductor) devices, the primary objective of the isolation barrier is to prevent parasitic current from flowing from the source of one device to the drain of an adjacent device. To illustrate, FIG. 1 shows a portion of a representative MOS IC circuit 100 comprising transistors 102, 104 and 106. Transistors 102 and 104 have in common a polysilicon gate 108 while transistor 106 is coupled to its own polysilicon gate 110. A polysilicon interconnect 112 is shown disposed between transistors 102 and 106.
Between transistors 102 and 104, there exists a conduction channel through which parasitic current may flow, thereby potentially forming an unwanted parasitic transistor. Likewise, the proximity of transistors 102 and 106 results in a conduction channel between these two transistors, undesirably creating another potential parasitic transistor. To prevent the formation of these parasitic transistors, isolation barriers between adjacent transistor pairs are preferably provided.
FIG. 2 shows one approach to providing isolation barriers between adjacent transistor pairs. In FIG. 2, the region between transistors 102 and 104 (shown as region 120) is preferably rendered relatively non-conductive to potential parasitic current flow by doping it with an appropriate dopant such as arsenic and phosphorous for N-channel devices, or boron for P-channel devices. Similarly, region 122 between transistor 102 and its adjacent transistors is likewise doped, as is region 124 between transistor 104 and its adjacent transistors.
The formation of unwanted conduction channels between adjacent transistors is further prevented by relatively thick silicon dioxide regions 126, 128, and 130. If the active devices are created in an epitaxial layer, e.g., in the case of bipolar devices, the silicon dioxide features, e.g., regions 126, 128, and 130, preferably extend into the substrate far enough to penetrate through the epitaxial layer.
Local oxidation of silicon (LOCOS) has proven in the past to be a cost-effective and efficient process for meeting these isolation requirements. LOCOS technology, being well known and extensively described in the literature, is familiar to those skilled in the art. In general, a typical LOCOS process involves growing a thin layer of thermal "pad" oxide, followed by the deposition of a silicon nitride thermal diffusion barrier. Openings in the nitride and oxide layers are then patterned and etched to expose the substrate, using a conventional photoresist process.
The exposed substrate regions are then doped via a conventional ion implantation technique to form "channel-stop" regions. As the term is used herein, a channel-stop region denotes a region of the substrate that has been rendered relatively non-conductive through doping or ion implantation to help prevent the formation of a conductive channel between adjacent transistors through which parasitic current can flow. Subsequent to the doping/implantation step, thick field oxide features are then grown. Isolation of adjacent active devices is achieved through a combination of the field oxide feature and the channel-stop region.
However, as the geometries of modem active devices decrease and are scaled with sub-micron or smaller design rules, it has been discovered that the basic LOCOS process has limitations that make application to the modern sub-micron geometries very difficult. For example, LOCOS cannot provide the necessary planarity for implementing multi-layer metallization schemes. This is because the uneven LOCOS surface produces a non-planar surface, which is then propagated through subsequent processes of metallization, inter-metal dielectric (IMD) formation, masking, via etching, and the like. As design rules become smaller and smaller, the consequences of the LOCOS uneven surface become more magnified.
Further, the LOCOS process exhibits a "field-oxide thinning" effect. This is because the oxide does not grow as quickly in a smaller width spacing as it does in a wider spacing. By way of example, FIG. 3 schematically illustrates an isolation barrier formed by the basic LOCOS process. Because of field-oxide thinning, oxide region 302 is thinner than oxide region 304 by a thickness denoted as D1 in FIG. 3. Depending on the width of the spacings, these variations in the oxide thickness produce a more uneven surface than usual. These variations in the oxide thickness in turn lead to variations in the threshold voltage, interconnect-to-substrate capacitance, and field-edge leakage, or the like.
It has also been found that the LOCOS process causes some field oxide to grow laterally and penetrate under the nitride-mask region, creating what is referred to in the art as bird's beaks. Further, ions implanted in the channel-stop layer may diffuse laterally, increasing the effective size of the channel-stop region over the original implant dimensions. The encroaching ion implantation region is shown as region 308 in FIG. 3. As design rules become smaller and smaller, a larger fraction of the die area is effectively wasted to accommodate the limitations imposed by the LOCOS bird's beaks and ion implant encroachments.
Trench fill isolation represents an alternative technique for forming isolation barriers. In trench fill isolation, a thin layer of pad oxide is grown on the substrate, and a thin layer of silicon nitride is deposited over the pad oxide. The films are then masked and etched to produce trenches, using a conventional photoresist process. By way of example, one such photoresist technique involves the application of a resist material, the exposure of the resist in a contact or stepper lithography system, and the development of the resist to form a mask to facilitate subsequent etching.
The result is shown in FIG. 4A, in which a trench 400 is etched through nitride layer 402 and pad oxide layer 404. Sometimes, ion implantation is used to produce a channel-stop layer in the substrate. This channel-stop layer is shown in FIG. 4B as channel-stop region 408.
A thin layer of thermal oxide 410 is then grown in trench 400 (FIG. 4C). A chemical vapor deposition (CVD) process then fills trench 400 with oxide in FIG. 4D to provide the isolation. Subsequent chemical mechanical polish (CMP) planarizes the geometry, yielding tight tolerances that make subsequent processing steps easier. Trench-fill isolation proves to be an improvement over LOCOS as it has no bird's beaks, channel-stop ion diffusion, or field-oxide thinning effects. Hence, the die area can be used much more efficiently to achieve high device density.
In the prior art, the trenches are typically filled using a plasma-enhanced chemical vapor deposition (PECVD) process. The prior art trench fill PECVD process is typically accomplished while the wafer is unbiased, resulting in a deposition of silicon dioxide that is fairly conformal. This conformal quality of the prior art trench-fill layer unfortunately often produces defects, which manifest themselves as voids or holes, in the filled trench. By way of example, FIG. 4D shows a void 430 in the filled trench, which is formed when trench-fill deposition pinches off the trench opening while filling it. Because of these defects, isolation barriers formed by the prior art trench fill deposition process have been found to be of low quality and unsuitable for modern narrow, deep trenches and high density devices.
In view of the above, what is needed is improved methods and apparatus for forming trench fill isolation barriers.